Semiconductor integrated circuit (IC) fabrication involves forming multiple material layers with designed patterns on a semiconductor wafer. Each layer has to be aligned with previous layers such that the formed circuit can function properly. Various marks are used for this purpose. For example, alignment marks are used for alignment between a photomask and the semiconductor wafer. In another example, overlay marks are used to monitor overlay deviation between the layers on the wafer. As semiconductor technology continues progressing to circuit layouts having smaller feature sizes, the alignment requirement becomes more stringent and the alignment/overlay marks are expected to take less wafer area. However, when a non-planar structure is utilized in the integrated circuit, the existing alignment method and the system is not capable of alignment monitoring and measuring with high accuracy. For example, a three dimensional devices, such as Fin-like field effect transistor (FinFET), is formed on a wafer, the existing alignment system with a single wavelength and the corresponding method are not capable of making proper alignment measurement. Especially, when the patterned structure is thinned down (or polished), the alignment signal is degraded. Accordingly, the wafer quality is degraded due to the misalignment. It is desired, therefore, to provide a method and a system for monitoring and controlling alignment and overlay with high measurement signal quality and (accordingly) high wafer quality.